MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1408

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Serial bit clock
Functional description
Ensure that the bit clock frequency (internally generated by dividing the network clock or
sourced from external device through Tx/Rx clock ports) is never greater than 1/5 of the
peripheral clock frequency.
In normal mode, the bit clock, used to serially clock the data, is visible on the serial
transmit clock (STCK) and serial receive clock (SRCK) ports. The word clock is an
internal clock used to determine when transmission of an 8, 10, 12, 16, 18, 20, 22 or 24
bit word has completed. The word clock then clocks the frame clock, which counts the
number of words in the frame. The frame clock can be viewed on the STFS and SRFS
frame sync ports, because a frame sync generates after the correct number of words in the
frame have passed. In master and synchronous mode, the SRCK port is used as serial
oversampling clock (network clock) enabled by the CR[SYSCLKEN] bit. This serial
system clock is an oversampling clock of the frame sync clock (STFS). In this mode, the
word length (WL), prescaler range (PSR), prescaler modulus (PM), and frame rate (DC)
selects the ratio of network clock to sampling clock, STFS. In I
oversampling clock network clock is available on this port if the CR[SYSCLKEN] bit is
set.
The following figure shows the relationship between the clocks and the dividers. The bit
clock can be received from an I
through a divider, as shown in
1408
• Bit clock — Serially clocks the data bits in and out of the I
• Word clock — Counts the number of data bits per word (8, 10, 12, 16, 18, 20, 22 or
• Frame clock (frame sync) — Counts the number of words in a frame. This signal can
• Master clock —In master mode, this is an integer multiple of frame clock. It is used
either generated internally or taken from external clock source (through the Tx/Rx
clock ports).
24 bits). This clock is generated internally from the bit clock.
be generated internally from the bit clock, or taken from external source (from the
Tx/Rx frame sync ports).
in cases when I
/18, /20, /22, /24)
(/8, /10, /12, /16,
2
S has to provide the clock.
Word divider
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure
2
Figure 46-55. I
S clock port or can be generated from the network clock
46-56.
Word clock
2
S clocking
Frame divider
(/1 to /32)
2
2
S port. This clock is
S mode, the
Freescale Semiconductor, Inc.
Frame clock