MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1102

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
42.4.3.4 Delay after Transfer (t
The Delay after Transfer is the minimum time between negation of the PCS signal for a
frame and the assertion of the PCS signal for the next frame. See
illustration of the Delay after Transfer. The PDT and DT fields in the CTARx registers
select the Delay after Transfer by the formula in the DT field description. The following
table shows an example of how to compute the Delay after Transfer.
When in non-continuous clock mode the t
equation specified in the CTAR[DT] bitfield description. When in continuous clock
mode, the delay is fixed at 1 SCK period.
42.4.3.5 Peripheral Chip Select Strobe Enable (PCSS )
The PCSS signal provides a delay to allow the PCS signals to settle after a transition
occurs thereby avoiding glitches. When the DSPI is in master mode and the PCSSE bit is
set in the MCR, PCSS provides a signal for an external demultiplexer to decode the
PCS[0] - PCS[4] signals into as many as 128 glitch-free PCS signals. The following
figure shows the timing of the PCSS signal relative to PCS signals.
The delay between the assertion of the PCS signals and the assertion of PCSS is selected
by the PCSSCK field in the CTAR based on the following formula:
1102
100 MHz
f
sys
PCSS
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
PCSx
Table 42-83. Delay after Transfer Computation Example
0b01
PDT
Figure 42-71. Peripheral Chip Select Strobe Timing
t
PCSSCK
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Prescaler
3
DT
NOTE
DT
)
0b1110
delay is configured according to the
DT
Scaler
32768
Figure 42-72
t
PASC
Freescale Semiconductor, Inc.
Delay after Transfer
0.98 ms
for an