MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 465

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The following figure shows how each DMA request initiates one minor-loop transfer, or
iteration, without CPU intervention. DMA arbitration can occur after each minor loop,
and one level of minor loop DMA preemption is allowed. The number of minor loops in
a major loop is specified by the beginning iteration count (BITER).
The following figure lists the memory array terms and how the TCD settings interrelate.
Freescale Semiconductor, Inc.
TCDn_CSR field
INT_HALF
INT_MAJ
ACTIVE
D_REQ
START
DONE
E_SG
name
BWC
Control bit to start channel explicitly when using a software initiated DMA service (Automatically
cleared by hardware)
Status bit indicating the channel is currently in execution
Status bit indicating major loop completion (cleared by software when using a software initiated
DMA service)
Control bit to disable DMA request at end of major loop completion when using a hardware initiated
DMA service
Control bits for throttling bandwidth control of a channel
Control bit to enable scatter-gather feature
Control bit to enable interrupt when major loop is half complete
Control bit to enable interrupt when major loop completes
Description
Figure 21-292. Example of multiple loop iterations
DMA request
DMA request
DMA request
Table 21-297. TCD Control and Status fields
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Source or destination memory
Chapter 21 Direct Memory Access Controller (eDMA)
count (CITER)
Current major
loop iteration
3
2
1
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