MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 520

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
24.3.6 MCG Control 6 Register (MCG_C6)
Address: MCG_C6 is 4006_4000h base + 5h offset = 4006_4005h
520
LOLIE
PLLS
VDIV
CME
Reset
Field
Read
4–0
Write
7
6
5
Bit
LOLIE
Loss of Lock Interrrupt Enable
Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect
when LOLS is set.
0
1
PLL Select
Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS
bit is cleared and PLLCLKEN is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is
disabled in all modes.
0
1
Clock Monitor Enable
Determines if a reset request is made following a loss of external clock indication. The CME bit should
only be set to a logic 1 when the MCG is in an operational mode that uses the external clock (FEE, FBE,
PEE, PBE, or BLPE). Whenever the CME bit is set to a logic 1, the value of the RANGE bits in the C2
register should not be changed. CME bit should be set to a logic 0 before the MCG enters any Stop
mode. Otherwise, a reset request may occur while in Stop mode. CME should also be set to a logic 0
before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
0
1
VCO Divider
Selects the amount to divide the VCO output of the PLL. The VDIV bits establish the multiplication factor
(M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN or
PLLS), the VDIV value must not be changed when LOCK is zero.
7
0
VDIV
00000
No interrupt request is generated on loss of lock.
Generate an interrupt request on loss of lock.
FLL is selected.
PLL is selected (PRDIV need to be programmed to the correct divider to generate a PLL reference
clock in the range of 2 - 4 MHz prior to setting the PLLS bit).
External clock monitor is disabled.
Generate a reset request on loss of external clock.
Multiply
Factor
24
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
PLLS
0
6
MCG_C6 field descriptions
Table continues on the next page...
CME
Table 24-9. PLL VCO Divide Factor
0
5
VDIV
01000
Multiply
Factor
32
0
4
Description
0
3
VDIV
10000
Multiply
Factor
40
VDIV
0
2
Freescale Semiconductor, Inc.
0
1
VDIV
11000
Multiply
Factor
48
0
0