MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 489

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

23.3 Functional Overview
The preceding figure shows the operation of the watchdog. The values for N and K are:
The watchdog is a fail safe mechanism that brings the system into a known initial state in
case of its failure due to CPU clock stopping or a run away condition in code execution.
In its simplest form, the watchdog timer runs continuously off a clock source and expects
Freescale Semiconductor, Inc.
Bus Clock
System
Alt Clock
LPO
Fast
Fn Test
Clock
Osc
• N = 256
• K = 20
WDOG
Disable Control/Configuration
bit changes N bus clk cycles after
unlocking
STOPEN
StandbyEN
WAITEN
DebugEN
N bus clk cycles
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
WDOGTEST
WDOGEN
CLKSRC
WDOGT
WINEN
WDOG
Figure 23-1. WDOG Operation
Selection
WDOG
Clock
0xC520
0xD928
Allow update for N bus
clk cycles
WDOG CLK
Window_begin
Unlock Sequence
2 Writes of data within K bus clock
cycles of each other
32-bit Modulus Reg
(Time-out Value)
32-bit Timer
WDOGEN = WDOG Enable
WINEN = Windowed Mode Enable
WDOGT = WDOG Time-out Value
WDOGCLKSRC = WDOG Clock Source
WDOG Test = WDOG Test Mode
WAIT EN = Enable in wait mode
STOP EN = Enable in stop mode
Standby EN = Enable in standby mode
Debug EN = Enable in debug mode
SRS = System Reset Status Register
R = Timer Reload
Chapter 23 Watchdog Timer (WDOG)
R
Timer Time-out
after unlocking
Invalid Refresh
Unlock Seq
No unlock
after reset
No config
Refresh
Outside
Window
Invalid
0xA602
0xB480
Seq
reset count
WDOG
Refresh Sequence
2 writes of data within K
bus clock cycles of each
other
IRQ_RST_
EN = = 1?
and SRS register
Y
N
System reset
Interrupt
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