MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1397

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

writing to the TX registers or ignoring the time slot as determined by TMSK register bits.
The receiver is treated in the same manner and received data is only transferred to the
receive data register/FIFO if the corresponding time slot is enabled through RMSK.
By using the TMSK and RMSK registers, software only has to service the I
valid time slots. This eliminates any overhead associated with unused time slots.
In the two-channel mode, the second set of transmit and receive FIFOs and data registers
create two separate channels. These channels are completely independent with their own
set of interrupts and DMA requests, which are identical to the ones available for the
default channel. In this mode, data is transmitted/received in enabled time slots
alternately from/to FIFO 0 and FIFO 1, starting from FIFO 0. The first data word is taken
from FIFO 0 and transmitted in the first enabled time slot and subsequently, data is
loaded from FIFO 1 and FIFO 0 alternately and transmitted. Similarly, the first received
data is sent to FIFO 0 and subsequent data is sent to FIFO 1 and FIFO 0 alternately. Time
slots are selected through the transmit and receive time slot mask registers (TMSK and
RMSK). For using this mode of operation, the CR[TCHEN] bit must be set.
46.4.1.2.1 Network mode transmit
The transmit portion of I
However, for continuous clock, when the CR[TE] bit is set, the transmitter is enabled
only after detection of a new frame sync (transmission starts from the next frame
boundary).
Normal start-up sequence for transmission:
Alternatively, the user may decide not to transmit in a time slot by configuring the
TMSK[STMSK]. The ISR[TDE] flag is cleared as data is shifted from TX register to
TXSR, but the STXD port remains disabled during the time slots. When the next frame
sync is detected or generated (continuous clock), the data word in TXSR and is shifted
out (transmitted). When the TX register is empty, the ISR[TDE] bit is set, which causes a
transmitter interrupt (in case the FIFO is disabled) to be sent if the TIE bit is set. Software
can poll the ISR[TDE] bit or use interrupts to reload the TX register with new data for the
Freescale Semiconductor, Inc.
1. Enable network mode
2. Enable I
3. Write the data to be transmitted to the TX register. This clears the ISR[TDE] flag
4. Set the CR[TE] bit to enable the transmitter on the next frame boundary (for
5. Enable transmit interrupts
continuous clock)
2
S
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
2
S is enabled when the CR[I2SEN and TE] bits are set.
Chapter 46 Integrated interchip sound (I2S)
2
S during
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