MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1103

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

At the end of the transfer the delay between PCSS negation and PCS negation is selected
by the PASC field in the CTAR based on the following formula:
The following table shows an example of how to compute the t
The following table shows an example of how to compute the t
The PCSS signal is not supported when Continuous Serial Communication SCK mode
are enabled.
42.4.4 Transfer Formats
The SPI serial communication is controlled by the Serial Communications Clock (SCK)
signal and the PCS signals. The SCK signal provided by the master device synchronizes
shifting and sampling of the data on the SIN and SOUT pins. The PCS signals serve as
enable signals for the slave devices.
In master mode, the CPOL and CPHA bits in the Clock and Transfer Attributes Registers
(CTARn) select the polarity and phase of the serial clock, SCK.
Even though the bus slave does not control the SCK signal, in slave mode these values
must be identical to the master device settings to ensure proper transmission. In SPI slave
mode, only CTAR0 is used.
Freescale Semiconductor, Inc.
• CPOL - Selects the idle state polarity of the SCK
• CPHA - Selects if the data on SOUT is valid before or on the first SCK edge
100 MHz
100 MHz
f
f
sys
sys
Table 42-85. Peripheral Chip Select Strobe Negate Computation Example
Table 42-84. Peripheral Chip Select Strobe Assert Computation Example
The clock frequency mentioned in the preceding tables is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
PCSSCK
PASC
0b11
0b11
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Prescaler
Prescaler
7
7
NOTE
Delay before Transfer
Delay after Transfer
pcssck
pasc
delay.
70.0 ns
70.0 ns
delay.
Chapter 42 SPI (DSPI)
1103