MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1296

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
45.5.1.1 Write operation sequence
There are three ways to write data into the buffer when the user transfers data to the card:
When the internal DMA is not used, (i.e. the XFERTYP[DMAEN] bit is not set when the
command is sent), the SDHC asserts a DMA request when the amount of buffer space
exceeds the value set in the WML register, and is ready for receiving new data. At the
same time, the SDHC would set the IRQSTAT[BWR] bit. The buffer write ready
interrupt will be generated if it is enabled by software.
When internal DMA is used, the SDHC will not inform the system before all the required
number of bytes are transferred (if no error was encountered). When an error occurs
during the data transfer, the SDHC will abort the data transfer and abandon the current
block. The host driver should read the contents of the DSADDR to get the starting
address of the abandoned data block. If the current data transfer is in multi block mode,
the SDHC will not automatically send CMD12, even though the XFERTYP[AC12EN]
bit is set. The host driver shall send CMD12 in this scenario and re-start the write
operation from that address. It is recommended that a software reset for data be applied
before the transfer is re-started after error recovery.
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Figure 45-28. Data swap between system bus and SDHC data buffer in byte little endian
1. By using external DMA through the SDHC DMA request signal.
2. By processor core polling through the IRQSTAT[BWR] bit (interrupt or polling).
3. By using the internal DMA.
Figure 45-29. Data swap between system bus and SDHC data buffer in half word big
System IP Bus or System AHB Bus
System IP Bus or System AHB Bus
SDHC Data buffer
SDHC Data buffer
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