MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1266

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map and register definition
45.4.12 System Control Register (SDHC_SYSCTL)
Address: SDHC_SYSCTL is 400B_1000h base + 2Ch offset = 400B_102Ch
1266
Reset
Reset
Bit
Bit
W
W
Reserved
R
R
31–28
RSTD
INITA
Field
Field
27
26
31
15
0
1
30
14
0
0
all these transactions. It is not necessary to change for each transaction. When the software issues
multiple SD commands, setting the bit once before the first command is sufficient: it is not necessary to
reset the bit between commands.
0b
1b
This read-only field is reserved and always has the value zero.
Initialization Active
When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks are sent, this bit is self cleared.
This bit is very useful during the card power-up period when 74 SD-clocks are needed and the clock auto
gating feature is enabled. Writing 1 to this bit when this bit is already 1 has no effect. Writing 0 to this bit at
any time has no effect. When either of the PRSSTAT[CIHB] and PRSSTAT[CDIHB] bits are set, writing 1
to this bit is ignored (i.e. when command line or data lines are active, write to this bit is not allowed). On
the otherhand, when this bit is set, i.e., during intialization active period, it is allowed to issue command,
and the command bit stream will appear on the CMD pad after all 80 clock cycles are done. So when this
command ends, the driver can make sure the 80 clock cycles are sent out. This is very useful when the
driver needs send 80 cycles to the card and does not want to wait till this bit is self cleared.
Software Reset For DAT Line
Only part of the data circuit is reset. DMA circuit is also reset.
The following registers and bits are cleared by this bit:
0
• Data port register
• Buffer is cleared and initialized.Present State register
• Buffer Read Enable
LED off
LED on
29
13
0
0
SDHC_PROCTL field descriptions (continued)
SDCLKFS
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
SDHC_SYSCTL field descriptions
27
11
0
0
Table continues on the next page...
RSTD
26
10
0
0
0
RSTC
25
0
0
0
9
RSTA
24
0
0
0
8
Description
Description
23
0
0
7
22
0
0
6
DVS
0
21
0
0
5
20
0
0
4
Freescale Semiconductor, Inc.
19
0
1
3
18
0
0
2
DTOCV
17
0
0
1
16
0
0
0