MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 578

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory map and register descriptions
27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)
The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered
0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes
the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 2.
Addresses: FMC_TAGVDW2S0 is 4001_F000h base + 140h offset = 4001_F140h
578
Bit
W
R
Reserved
Reserved
31
0
tag[18:6]
31–19
18–6
Field
valid
5–1
30
0
0
FMC_TAGVDW2S1 is 4001_F000h base + 144h offset = 4001_F144h
FMC_TAGVDW2S2 is 4001_F000h base + 148h offset = 4001_F148h
FMC_TAGVDW2S3 is 4001_F000h base + 14Ch offset = 4001_F14Ch
FMC_TAGVDW2S4 is 4001_F000h base + 150h offset = 4001_F150h
FMC_TAGVDW2S5 is 4001_F000h base + 154h offset = 4001_F154h
FMC_TAGVDW2S6 is 4001_F000h base + 158h offset = 4001_F158h
FMC_TAGVDW2S7 is 4001_F000h base + 15Ch offset = 4001_F15Ch
29
0
28
0
This read-only field is reserved and always has the value zero.
13-bit tag for cache entry
This read-only field is reserved and always has the value zero.
1-bit valid for cache entry
27
0
26
0
25
0
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
FMC_TAGVDW2Sn field descriptions
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
tag[18:6]
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
4
0
0
0
3
0
2
0
1
0
0