MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1141

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
43.4.2 10-bit Address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte.
Various combinations of read/write formats are possible within a transfer that includes
10-bit addressing.
43.4.2.1 Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed. When a 10-bit address follows a START condition,
each slave compares the first seven bits of the first byte of the slave address (11110XX)
with its own address and tests whether the eighth bit (R/W direction bit) is 0. It is
possible that more than one device finds a match and generates an acknowledge (A1).
Each slave that finds a match compares the eight bits of the second byte of the slave
address with its own address, but only one slave finds a match and generate an
acknowledge (A2). The matching slave remains addressed by the master until it receives
a STOP condition (P) or a repeated START condition (Sr) followed by a different slave
address.
Freescale Semiconductor, Inc.
(hex)
ICR
S
1C
1D
1A
1B
1E
1F
19
Table 43-42. Master-Transmitter Addresses Slave-Receiver with a 10-bit
s first 7
addres
11110
Slave
AD10
+ AD9
bits
+
Divider
SCL
112
128
144
160
192
240
96
R/W
Table 43-41. I2C Divider and Hold Values (continued)
0
SDA Hold
Value
17
17
25
25
33
33
Address
9
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
A1
SCL Hold
(Start)
Value
118
46
54
62
70
78
94
second
AD[8:1]
addres
Slave
byte
s
SCL Hold
(Stop)
Value
121
49
57
65
73
81
97
A2
Data
(hex)
ICR
3A
3B
3C
3D
3E
39
3F
A
(clocks)
Divider
1536
1792
2048
2304
2560
3072
3840
SCL
Chapter 43 Inter-Integrated Circuit (I2C)
...
SDA Hold
(clocks)
129
257
257
385
385
513
513
Data
SCL Hold
(Start)
Value
1022
1150
1278
1534
1918
766
894
A/A
SCL Hold
(Stop)
Value
1025
1153
1281
1537
1921
769
897
P
1141

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