MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 178

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Boot
reprogram the option byte in flash to change the FOPT values that are used for
subsequent resets. For more details on programming the option byte, refer to the flash
memory chapter.
The MCU uses the FTFL_FOPT register bits to configure the device at reset as shown in
the following table.
6.3.4 Boot sequence
At power up, the on-chip regulator holds the system in a POR state until the input supply
is above the POR threshold. The system continues to be held in this static state until the
internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The Mode Controller reset logic then controls a sequence to exit reset.
178
7-2
1
0
Num
1. A system reset is held on internal logic, the RESET pin is driven out low, and the
2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus
3. The system reset on internal logic continues to be held, but the Flash Controller is
Bit
MCG is enabled in its default clocking mode.
Clocks that do not have clock gate control).
released from reset and begins initialization operation while the Mode Control logic
continues to drive the RESET pin out low for a count of ~128 Bus Clock cycles.
Reserved
EZPORT_DIS
LPBOOT
Field
Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
1
0
1
Value
Reserved for future expansion.
EzPort operation is disabled. The device always boots to normal CPU execution
and the state of EZP_CS signal during reset is ignored. This option avoids
inadvertent resets into EzPort mode if the EZP_CS/NMI pin is used for its NMI
function.
EzPort operation is enabled. The state of EZP_CS pin during reset determines if
device enters EzPort mode.
Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured
at reset exit for higher divide values that produce lower power consumption at
reset exit.
Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at
reset exit for higher frequency values that produce faster operating frequencies at
reset exit.
• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2)
• Flash clock divider (OUTDIV4)is 0xF (divide by 16)
• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2)
• Flash clock divider (OUTDIV4)is 0x1 (divide by 2)
are 0x7 (divide by 8)
are 0x0 (divide by 1)
Definition
Freescale Semiconductor, Inc.