MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 491

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The update feature is useful for applications that have an initial, non-safety critical part,
where the watchdog is kept disabled or with a conveniently long time-out period. This
means the application coder does not have to bother with frequently servicing the
watchdog. After the critical part of the application begins, the watchdog can be
reconfigured as per need.
The watchdog issues a reset (or interrupt-then-reset if enabled) to the system for any of
these invalid unlock sequences:
Also, an attempted refresh operation between the two writes of the unlock sequence and
in the WCT time following a successful unlock, goes undetected. Also, see
Operation with 8-bit access
23.3.2 The Watchdog Configuration Time (WCT)
To prevent unintended modification of the watchdog's control and configuration register
bits, you are allowed to update them only within a period of 256 bus clock cycles after
unlocking. This window period is known as the watchdog configuration time (WCT). In
addition, these register bits can be modified only once after unlocking them for editing
(even after reset).
You must unlock the registers within WCT time after system reset, failing which the
WDOG issues a reset to the system. To be more precise, you must write at least the first
word of the unlocking sequence within the WCT time after reset. Once this is done, you
get a further 20 bus clock cycles (the maximum allowed gap between the words of the
unlock sequence) to complete the unlocking operation. Thereafter, to make sure that you
do not forget to configure the watchdog, the watchdog issues a reset if none of the
WDOG control and configuration registers is updated in the WCT time after unlock.
After the close of this window or after the first write, these register bits are locked out
from any further changes.
The watchdog timer keeps running as per its default configuration through unlocking and
update operations that can extend up to a maximum total of 2xWCT time + 20 bus clock
cycles. Therefore, it must be ensured that the time-out value for the watchdog is always
greater than 2xWCT time + 20 bus clock cycles.
Freescale Semiconductor, Inc.
• You write any value other than 0xC520 or 0xD928 to the unlock register.
• ALLOW_UPDATE is set and you allow a gap of more than 20 bus clock cycles
between the writing of the unlock sequence values.
A context switch during unlocking and refreshing may lead to a
watchdog reset.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
for guidelines related to 8-bit accesses to the unlock register.
Note
Chapter 23 Watchdog Timer (WDOG)
Watchdog
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