MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 871

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

In the case of legacy PWM synchronization, the MOD register synchronization depends
on PWMSYNC and REINIT bits according to the following description.
If (SYNCMODE = 0), (PWMSYNC = 0) and (REINIT = 0) then this synchronization is
made on the next selected loading point after an enabled trigger event takes place. If the
trigger event was a software trigger then the SWSYNC bit is cleared on the next selected
Freescale Semiconductor, Inc.
PWM synchronization
legacy
updated by software trigger
wait the next selected
clear SWSYNC bit
update MOD with
FTM counter is reset by
its buffer value
MOD register is
loading point
software trigger
end
0
Figure 36-208. MOD Register Synchronization Flowchart
=
0
=
SWRSTCNT
SWWRBUF
SWSYNC
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
bit ?
bit ?
bit ?
= 1
= 1
software
clear SWSYNC bit
trigger
update MOD with
its buffer value
= 0
= 1
end
end
0
=
SYNCMODE
begin
bit ?
updated by hardware trigger
wait the next selected
= 1
update MOD with
MOD register is
its buffer value
loading point
FTM counter is reset by
hardware trigger
end
enhanced PWM synchronization
wait hardware trigger n
0 =
0 =
HWTRIGMODE
clear TRIGn bit
HWRSTCNT
HWWRBUF
TRIGn
bit ?
bit ?
bit ?
bit ?
= 1
= 1
= 0
Chapter 36 FlexTimer (FTM)
hardware
trigger
update MOD with
its buffer value
= 0
= 1
= 1
end
end
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