MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 234

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory map and register definition
11.4.1 Pin Control Register n (PORTx_PCRn)
For PCR1 to PCR5 of the port A, bit 0, 1, 6, 8, 9,10 reset to 1; for the PCR0 of the port
A, bit 1, 6, 8, 9, 10 reset to 1; in other conditions, all bits reset to 0.
Addresses: 4004_9000h base + 0h offset + (4d × n), where n = 0d to 31d
234
Bit
W
R
4004_D0A0
4004_D0C0
4004_D0C4
4004_D0C8
Absolute
address
Reserved
Reserved
(hex)
31
0
31–25
23–20
19–16
IRQC
Field
ISF
24
30
0
29
0
Interrupt Status Flag Register (PORTE_ISFR)
Digital Filter Enable Register (PORTE_DFER)
Digital Filter Clock Register (PORTE_DFCR)
Digital Filter Width Register (PORTE_DFWR)
28
0
0
This read-only field is reserved and always has the value zero.
Interrupt Status Flag
The pin interrupt configuration is valid in all digital pin muxing modes.
0
1
This read-only field is reserved and always has the value zero.
Interrupt Configuration
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured
to generate interrupt / DMA Request as follows:
0000
0001
0010
0011
0100
1000
27
0
Configured interrupt has not been detected.
Configured interrupt has been detected. If pin is configured to generate a DMA request then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer,
otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive
interrupt that remains asserted then flag will set again immediately.
26
0
25
0
Interrupt/DMA Request disabled.
DMA Request on rising edge.
DMA Request on falling edge.
DMA Request on either edge.
Reserved.
Interrupt when logic zero.
w1c
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
Register name
22
0
PORTx_PCRn field descriptions
PORT memory map (continued)
0
21
0
Table continues on the next page...
20
0
19
0
18
IRQC
0
17
0
16
0
15
0
Description
14
0
13
0
0
12
0
(in bits)
Width
32
32
32
32
11
0
10
0
MUX
Access
0
9
R/W
R/W
R/W
w1c
0
8
Freescale Semiconductor, Inc.
0
0
7
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0
6
0
5
4
0
0
0
3
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Section/
0
2
page
0
1
0
0