MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1167

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

44.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Addresses: UART0_C2 is 4006_A000h base + 3h offset = 4006_A003h
Freescale Semiconductor, Inc.
Field
Reset
Read
ILT
Write
PE
PT
2
1
0
Bit
UART1_C2 is 4006_B000h base + 3h offset = 4006_B003h
UART2_C2 is 4006_C000h base + 3h offset = 4006_C003h
UART3_C2 is 4006_D000h base + 3h offset = 4006_D003h
TIE
Idle Line Type Select
ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins
either after a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic
1s preceding the stop bit can cause false recognition of an idle character. Beginning the count after the
stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
NOTE: In the case where UART is programmed with ILT = 1, a logic of 1'b0 is automatically shifted after
NOTE: In the case where UART is programmed for IDLE line wakeup (RWU = 1 and WAKE = 0), ILT
0
1
Parity Enable
Enables the parity function. When parity is enabled, parity function inserts a parity bit in the bit position
immediately preceding the stop bit. This bit must be set when 7816E is set/enabled.
0
1
Parity Type
PT determines whether the UART generates and checks for even parity or odd parity. With even parity,
an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an
odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.This bit must be
cleared when 7816E is set/enabled.
0
1
7
0
Idle character bit count starts after start bit.
Idle character bit count starts after stop bit.
Parity function disabled.
Parity function enabled.
Even parity.
Odd parity.
a received stop bit thus resetting the idle count.
has no effect on when the receiver starts counting logic 1s as idle character bits. In idle line
wakeup an idle character is recognized at anytime the receiver sees 10, 11, or 12 1s depending
on the M, PE, and C4[M10] bits.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
TCIE
UARTx_C1 field descriptions (continued)
0
6
RIE
0
5
Chapter 44 Universal Asynchronous Receiver/Transmitter (UART)
ILIE
0
4
Description
TE
0
3
RE
0
2
RWU
0
1
SBK
0
0
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