MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 94

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memories and Memory Interfaces
3.5.1.7 FTFL_FOPT Register
The flash memory's FTFL_FOPT register allows the user to customize the operation of
the MCU at boot time. See
3.5.2 Flash Memory Controller Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
94
1. Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for
2. Via the SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set
System memory map
Register access
Full description
more details.
to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared
when the mass erase completes.
Transfers
Transfers
Transfers
Clocking
Topic
Figure 3-22. Flash memory controller configuration
Table 3-36. Reference links to related information
Peripheral bridge
Related module
Crossbar switch
Flash memory
Flash memory
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
controller
MPU
FOPT boot options
Transfers
Flash memory
Peripheral bus
controller
controller 0
for details of its definition.
Register
access
Flash memory controller
System memory map
Clock Distribution
Peripheral bridge
Crossbar Switch
Flash memory
Reference
Transfers
MPU
Freescale Semiconductor, Inc.