MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1368

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map/register definition
1368
RFF1
RFF0
TFE1
Field
RLS
TLS
5
4
3
2
1
Transmit Last Time Slot.
This flag indicates the last time slot in a frame. When set, it indicates that the current time slot is the last
time slot of the frame. TLS is set at the start of the last transmit time slot and causes the I
interrupt (if IER[TIE] and TLSEN are set). TLS is not generated when frame rate is 1 in normal mode of
operation. TLS is cleared when the ISR is read with this bit set. The TLS bit is cleared by POR and I
reset.
0
1
Receive Last Time Slot.
This flag indicates the last time slot in a frame. When set, it indicates that the current time slot is the last
receive time slot of the frame. RLS is set at the end of the last time slot and causes the I
interrupt (if IER[RIE] and IER[RLSEN] are set). RLS is cleared when the ISR is read with this bit set. The
RLS bit is cleared by POR and I
0
1
Receive FIFO Full 1.
This flag is set when Rx FIFO1 is enabled, the data level in Rx FIFO1 reaches the selected Rx FIFO
WaterMark 1 (RFWM1) threshold and the I
interrupt when IER[RIE] and IER[RFF1EN] are set, Rx FIFO1 is enabled and the two-channel mode is
selected. RFF1 is automatically cleared when the amount of data in Rx FIFO1 falls below the threshold.
The RFF1 bit is cleared by POR and I
When Rx FIFO1 contains 15 words, the maximum it can hold, all further data received (for storage in this
FIFO) is ignored until the FIFO contents are read.
0
1
Receive FIFO Full 0.
This flag is set when Rx FIFO0 is enabled and the data level in Rx FIFO0 reaches the selected Rx FIFO
WaterMark 0 (RFWM0) threshold. The setting of RFF0 only causes an interrupt when IER[RIE] and
IER[RFF0EN] are set and Rx FIFO0 is enabled. RFF0 is automatically cleared when the amount of data
in Rx FIFO0 falls below the threshold. The RFF0 bit is cleared by POR and I
When Rx FIFO0 contains 15 words, the maximum it can hold, all further data received (for storage in this
FIFO) is ignored until the FIFO contents are read.
0
1
Transmit FIFO Empty 1.
This flag is set when the empty slots in Tx FIFO exceed or are equal to the selected Tx FIFO WaterMark
1 (TFWM1) threshold and the two-channel mode is selected. The setting of TFE1 only causes an interrupt
when IER[TIE] and IER[TFE1EN] are set, Tx FIFO1 is enabled and two-channel mode is selected. The
TFE1 bit is automatically cleared when the data level in Tx FIFO1 becomes more than the amount
specified by the watermark bits. The TFE1 bit is set by POR and I
0
1
Current time slot is not last time slot of frame.
Current time slot is the last transmit time slot of frame.
Current time slot is not last time slot of frame.
Current time slot is the last receive time slot of frame.
Space available in receive FIFO1.
Receive FIFO1 is full.
Space available in receive FIFO0.
Receive FIFO0 is full.
Transmit FIFO1 has data for transmission.
Transmit FIFO1 is empty.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
I2Sx_ISR field descriptions (continued)
Table continues on the next page...
2
S reset.
2
S reset.
2
S is in two-channel mode. The setting of RFF1 only causes an
Description
2
S reset.
2
Freescale Semiconductor, Inc.
S reset.
2
S to issue an
2
S to issue an
2
S