MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 182

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Power modes
182
Leakage Stop)
Wait) -via WFI
Normal Stop -
Normal Wait -
Stop)-via WFI
Low Leakage
Low Leakage
Low Leakage
VLLS3 (Very
VLLS2 (Very
VLLS1 (Very
VLPW (Very
VLPR (Very
VLPS (Very
Chip mode
Low Power
Low Power
Low Power
LLS (Low
via WFI
via WFI
Stop3)
Stop2)
Stop1)
Run)
Allows peripherals to function while the core is in sleep mode,
reducing power. NVIC remains sensitive to interrupts; peripherals
continue to be clocked.
Places chip in static state. Lowest power mode that retains all
registers while maintaining LVD protection. NVIC is disabled; AWIC is
used to wake up from interrupt; peripheral clocks are stopped.
On-chip voltage regulator is in a low power mode that supplies only
enough power to run the chip at a reduced frequency. Reduced
frequency Flash access mode (1 MHz); LVD off; internal oscillator
provides a low power 2 MHz source for the core, the bus and the
peripheral clocks.
Same as VLPR but with the core in sleep mode to further reduce
power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency.
Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional. Peripheral clocks are stopped,
but LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled
(FCLK = OFF); AWIC is used to wake up from interrupt. On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency. All SRAM is operating
(content retained and I/O states held).
State retention power mode. Most peripherals are in state retention
mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI,
DAC can be used. NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by the interrupt
All SRAM is operating (content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
Description
Table 7-1. Chip power modes (continued)
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Core mode
Freescale Semiconductor, Inc.
Sleep
Sleep
Run
Wakeup Reset
Wakeup Reset
Wakeup Reset
Interrupt
recovery
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Wakeup
method
Normal
1
2
2
2