MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 933

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

38.2.1 Detailed signal descriptions
38.3 Memory map and register definition
Freescale Semiconductor, Inc.
4004_000C
4004_0000
4004_0004
4004_0008
Absolute
address
(hex)
LPTMR_ALTn
Signal
Low Power Timer Control Status Register (LPTMR0_CSR)
Low Power Timer Prescale Register (LPTMR0_PSR)
Low Power Timer Compare Register (LPTMR0_CMR)
Low Power Timer Counter Register (LPTMR0_CNR)
The LPTMR registers are reset only on a POR or LVD event.
See
Table 38-2. LPTMR interface-detailed signal descriptions
LPTMR power and reset
I/O
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
I
Pulse counter input.
The LPTMR can select one of the input pins to be used in pulse counter mode.
Register name
State meaning
LPTMR memory map
Timing
NOTE
for more details.
Assertion-If configured for pulse counter mode with active
high input then assertion causes the LPTMR counter
register to increment.
Negation-If configured for pulse counter mode with active
low input then negation cause the LPTMR counter
register to increment.
Assertion or negation may occur at any time; input may
assert asynchronously to the bus clock.
Description
(in bits)
Width
32
32
32
32
Chapter 38 Low power timer (LPTMR)
Access
R/W
R/W
R/W
R
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
Section/
38.3.1/
38.3.2/
38.3.3/
38.3.4/
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