MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 436

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map/register definition
21.3.14 Error Register (DMA_ERR)
The ERR provides a bit map for the 16 channels, signaling the presence of an error for
each channel. The eDMA engine signals the occurrence of an error condition by setting
the appropriate bit in this register. The outputs of this register are enabled by the contents
of the EEI, and then routed to the interrupt controller. During the execution of the
interrupt-service routine associated with any DMA errors, it is software’s responsibility
to clear the appropriate bit, negating the error-interrupt request. Typically, a write to the
CERR in the interrupt-service routine is used for this purpose. The normal DMA channel
completion indicators (setting the transfer control descriptor DONE flag and the possible
assertion of an interrupt request) are not affected when an error is detected.
The contents of this register can also be polled because a non-zero value indicates the
presence of a channel error regardless of the state of the EEI. The state of any given
channel’s error indicators is affected by writes to this register; it is also affected by writes
to the CERR. On writes to the ERR, a one in any bit position clears the corresponding
channel’s error status. A zero in any bit position has no affect on the corresponding
channel’s current error status. The CERR is provided so the error indicator for a single
channel can easily be cleared.
Address: DMA_ERR is 4000_8000h base + 2Ch offset = 4000_802Ch
436
Reset
Reset
Bit
Bit
W
W
Reserved
R
R
31–16
Field
w1c
31
15
0
0
w1c
30
14
0
0
This read-only field is reserved and always has the value zero.
w1c
29
13
0
0
w1c
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
w1c
27
11
0
0
DMA_ERR field descriptions
Table continues on the next page...
w1c
26
10
0
0
w1c
25
0
0
9
w1c
24
0
0
8
0
Description
w1c
23
0
0
7
w1c
22
0
0
6
w1c
21
0
0
5
w1c
20
0
0
4
Freescale Semiconductor, Inc.
w1c
19
0
0
3
w1c
18
0
0
2
w1c
17
0
0
1
w1c
16
0
0
0