MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 961

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The activation of modulation space period is done when the carrier signal is low to
prohibit cutting off the high pulse of a carrier signal. If the carrier signal is high, the
modulator extends the mark period until the carrier signal become low. To de-assert the
space period and assert the mark period, the carrier signal must have gone low to assure
that a space period is not erroneously shortened.
Should the contents of the modulation space period register be all zeroes, the match will
be immediate and no space period will be generated (for instance, for FSK protocols that
require successive bursts of different frequencies).
MSC[MCGEN] must be set to enable the modulator timer.
39.7.3.1 Time Mode
When the modulator operates in time mode (MSC[MCGEN] bit is set, MSC[BASE] and
MSC[FSK] bits are cleared), the modulation mark period consists of an integer number of
CMTCLK ÷ 8 clock periods. The modulation space period consists of zero or an integer
number of CMTCLK ÷ 8 clock periods. With an 8 MHz IF and MSC[CMTDIV] = 00,
the modulator resolution is 1 μs and has a maximum mark and space period of about
65.535 ms each . See the following figure for an example of the time mode and baseband
mode outputs.
The mark and space time equations for time and baseband mode are:
Freescale Semiconductor, Inc.
0
* DENOTES HIDDEN REGISTER
SPACE PERIOD REGISTER *
17-BIT DOWN COUNTER *
CMTCMD1:CMTCMD2
CMTCMD3:CMTCMD4
1 6 B IT S
1 6 B IT S
=?
1 6
1 6
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure 39-16. Modulator Block Diagram
L O A D
SYSTEM CONTROL
CLOCK CONTROL
M O D E
MODULATOR GATE
Chapter 39 Carrier Modulator Transmitter (CMT)
MODULE INTERRUPT REQUEST
P R IM A R Y /S E C O N D A R Y S E L E C T
EOC FLAG SET
8
CARRIER OUT (f cg )
CMTCLOCK
MODULATOR
OUT
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