MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 295

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

If the MCU is configured for a disallowed power mode, the MCU remains in its current
power mode. For example, if in normal run (RUNM = 00, AVLP = 0) an attempt to enter
VLPR using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b indicating
MCU is still in normal run mode.
PMPROT is write once after any reset. This write to PMPROT clears LPLLSM, which
provides protection after wakeup from low power or low leakage modes. The state of
LPLLSM prior to clearing due to update of PMPROT indicates which power mode was
exited and should be used by initialization software for proper power mode recovery.
Address: MC_PMPROT is 4007_E000h base + 2h offset = 4007_E002h
Freescale Semiconductor, Inc.
Reserved
Reserved
AVLLS3
AVLP
ALLS
Reset
Field
Read
7–6
Write
5
4
3
2
Bit
The reset value of this register depends on the reset type:
This read-only field is reserved and always has the value zero.
Allow very low power modes
Provided the appropriate control bits are set up in PMCTRL, this write-once bit allows the MCU to enter
the very low power modes: VLPR, VLPW, and VLPS.
0
1
Allow low leakage stop mode
This write once bit allows the MCU to enter low leakage stop mode (LLS) provided the appropriate control
bits are set up in PMCTRL.
0
1
This read-only field is reserved and always has the value zero.
Allow Very Low Leakage Stop 3 Mode
This write once bit allows the MCU to enter very low leakage stop 3 mode (VLLS3) provided the
appropriate control bits are set up in PMCTRL.
7
0
• Low-leakage wake-up (LLS exit via RESET pin or any exit
• Other reset — 0x00
VLPR, VLPW, and VLPS are not allowed
VLPR, VLPW, and VLPS are allowed
LLS is not allowed
LLS is allowed
from VLLS) — bits 4, 2-0 unaffected
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
6
MC_PMPROT field descriptions
Table continues on the next page...
AVLP
0
5
NOTE
ALLS
0
4
Description
0
0
3
AVLLS3
0
2
Chapter 13 Mode Controller
AVLLS2
0
1
AVLLS1
0
0
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