MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1373

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
46.3.8 I
The TCR directs the transmit operation of the I2S. A power-on reset clears all TCR bits.
However, I2S reset does not affect the TCR bits.
Addresses: I2S0_TCR is 4002_F000h base + 1Ch offset = 4002_F01Ch
Freescale Semiconductor, Inc.
Bit
W
R
Reserved
31
0
TXBIT0
TFEN1
TFEN0
TFDIR
31–10
Field
30
9
8
7
6
0
29
0
2
28
S Transmit Configuration Register (I2Sx_TCR)
0
This read-only field is reserved and always has the value zero.
Transmit Bit 0.
This control bit allows I
register. The shifting data direction can be MSB or LSB first, controlled by the TCR[TSHFD] bit.
0
1
Transmit FIFO Enable 1.
This bit enables transmit FIFO 1. When enabled, the FIFO allows 15 samples to be transmitted by the I
(per channel) (a 9th sample can be shifting out) before TDE1 bit is set. When the FIFO is disabled, an
interrupt is generated when a single sample is transferred to the transmit shift register (provided the
interrupt is enabled).
0
1
Transmit FIFO Enable 0.
This bit enables transmit FIFO 0. When enabled, the FIFO allows 15 samples to be transmitted by the I
per channel (a 9th sample can be shifting out) before TDE0 bit is set. When the FIFO is disabled, an
interrupt is generated when a single sample is transferred to the transmit shift register (provided the
interrupt is enabled).
0
1
Transmit Frame Direction.
This bit controls the direction and source of the transmit frame sync signal. Internally generated frame
sync signal is sent out through the STFS port and external frame sync is taken from the same port.
0
1
27
0
Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or
12) of transmit shift register (MSB aligned).
Shifting with respect to bit 0 of transmit shift register (LSB aligned).
Transmit FIFO 1 disabled.
Transmit FIFO 1 enabled.
Transmit FIFO 0 disabled.
Transmit FIFO 0 enabled.
Frame sync is external.
Frame sync generated internally.
26
0
25
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
22
0
2
21
0
I2Sx_TCR field descriptions
S to transmit the data word from bit position 0 or 15/31 in the transmit shift
0
Table continues on the next page...
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
12
0
Chapter 46 Integrated interchip sound (I2S)
11
0
10
0
1
9
0
8
0
7
0
6
0
5
4
0
0
3
0
2
0
1
1373
2
2
S
S
0
0