MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1261

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
SDSTB
CDIHB
Field
DLA
3
2
1
0b
1b
SD Clock Stable
This status bit indicates that the internal card clock is stable. This bit is for the host driver to poll clock
status when changing the clock frequency. It is recommended to clear SYSCTL[SDCLKEN] bit to remove
glitch on the card clock when the frequency is changing.
0b
1b
Data Line Active
This status bit indicates whether one of the DAT lines on the SD bus is in use.
In the case of read transactions:
This status indicates if a read transfer is executing on the SD bus. Changes in this value from 1 to 0,
between data blocks, generates a block gap event interrupt in the interrupt status register.
This bit will be set in either of the following cases:
This bit will be cleared in either of the following cases:
The SDHC will wait at the next block gap by driving read wait at the start of the interrupt cycle. If the read
wait signal is already driven (data buffer cannot receive data), the SDHC can wait for a current block gap
by continuing to drive the read wait signal. It is necessary to support read wait in order to use the
suspend / resume function. This bit will remain 1 during read wait.
In the case of write transactions:
This status indicates that a write transfer is executing on the SD bus. Changes in this value from 1 to 0
generate a transfer complete interrupt in the interrupt status register.
This bit will be set in either of the following cases:
This bit will be cleared in either of the following cases:
In the case of command with busy pending:
This status indicates that a busy state follows the command and the data line is in use. This bit will be
cleared when the DAT0 line is released.
0b
1b
Command Inhibit (DAT)
1. When the end bit of the last data block is sent from the SD bus to the SDHC.
2. When the read wait state is stopped by a suspend command and the DAT2 line is released.
• After the end bit of the read command.
• When writing a 1 to the PROCTL[CREQ] to restart a read transfer.
• After the end bit of the write command.
• When writing to 1 to the PROCTL[CREQ] to continue a write transfer.
• When the SD card releases write busy of the last data block, the SDHC will also detect if the output
• When the SD card releases write busy, prior to waiting for write transfer, and as a result of a stop at
Bus clock is active
Bus clock is gated off
Clock is changing frequency and not stable
Clock is stable
DAT line inactive
DAT line active
is not busy. If the SD card does not drive the busy signal after the CRC status is received, the
SDHC shall assume the card drive “Not busy”.
block gap request.
SDHC_PRSSTAT field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Chapter 45 Secured digital host controller (SDHC)
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