MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 327
MK30DN512ZVLK10
Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet
1.MK30DN512ZVLK10.pdf
(1547 pages)
Specifications of MK30DN512ZVLK10
Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT
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16.2.3 SRAM arbitration and protection (MCM_SRAMAP)
The SRAMAP register defines the arbitration and protection schemes for the two SRAM
arrays.
Address: MCM_SRAMAP is E008_0000h base + Ch offset = E008_000Ch
Freescale Semiconductor, Inc.
Reset
Reset
SRAMLWP
SRAMLAP
Bit
Bit
Reserved
W
W
Reserved
R
R
29–28
15–8
AMC
Field
Field
7–0
31
30
31
15
0
0
0
30
14
Bits 23-0 are undefined after reset.
0
0
This read-only field is reserved and always has the value zero.
Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port.
0
1
This read-only field is reserved and always has the value zero.
SRAM_L write protect
When this bit is set, writes to SRAM_L array generates a bus error.
SRAM_L arbitration priority
Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the
SRAM_L array.
00
A bus master connection to AXBS input port n is absent
A bus master connection to AXBS input port n is present
SRAMLAP
29
13
Round robin
0
0
Reserved
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
MCM_SRAMAP field descriptions
27
11
0
0
0
MCM_PLAMC field descriptions
Table continues on the next page...
26
10
0
0
SRAMUAP
25
0
0
9
NOTE
24
0
0
8
Description
Description
23
0
0
7
Chapter 16 Miscellaneous Control Module (MCM)
22
0
0
6
21
0
0
5
Reserved
Reserved
20
0
0
4
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
327
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