MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1294

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
45.5 Functional description
The following sections provide a brief functional description of the major system blocks,
including the data buffer, DMA crossbar switch interface, dual-port memory wrapper,
data/command controller, clock & reset manager and clock generator.
45.5.1 Data buffer
The SDHC uses one configurable data buffer, so that data can be transferred between the
system bus and the SD card, with an optimized manner to maximize throughput between
the two clock domains (that is, the IP peripheral clock, and the master clock). The
following diagram illustrates the buffer scheme. The buffer is used as temporary storage
for data being transferred between the host system and the card. The watermark levels for
read and write are both configurable, and can be any number from 1 to 128 words. The
burst lengths for read and write are also configurable, and can be any number from 1 to
31 words.
There are 3 transfer modes to access the data buffer:
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• CPU polling mode:
• For a host read operation, when the number of words received in the buffer
meets or exceeds the RDWML watermark value, then by polling the
IRQSTAT[BRR] bit the host driver can read the DATPORT register to fetch the
amount of words set in the WML register from the buffer. The write operation is
similar.
Register
AHB
Bus
Bus
I/F
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure 45-27. SDHC buffer scheme
Internal
DMA
SDHC Registers
Buffer Control
Wrapper
Buffer
RAM
Tx / Rx
Status
FIFOs
Sync
FIFO
Sync
SD Bus
Freescale Semiconductor, Inc.
I/F