MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 174

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
The LVD can be configured to generate a reset upon detection of a low voltage condition
by setting LVDSC1[LVDRE]. After an LVD reset has occurred, the LVD system holds
the MCU in reset until the supply voltage rises above the low voltage detection threshold.
The SRSL[LVD] bit is set following an LVD reset or POR.
6.2.2.3 Computer operating properly (COP) watchdog reset
The watchdog timer monitors the operation of the system by expecting periodic
communication from the software, generally known as servicing (or refreshing) the
watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset.
The COP reset causes the SRSL[COP] bit to set.
6.2.2.4 Low leakage wakeup (LLWU) reset
The LLWU allows up to 16 external pins, the RESET pin, and up to seven internal
peripherals to wake the MCU from LLS and VLLSx power modes. The LLWU module is
only functional in LLS and VLLSx power modes. In both these modes, LLS mode exits
via RESET pin and any VLLS mode exits via a wakeup or reset event, the
SRSL[WAKEUP] bit in mode controller module is set indicating the low leakage mode
was active prior to the last system reset flow. Using the RESET pin to trigger an exit
from LLS or VLLS results in the SRSL[PIN] bit being set as well. Refer to the mode
controller chapter for more details.
After a system reset, the LLWU retains the flags to indicate the source of the last wakeup
until the user clears them.
6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) reset
The MCG includes a clock monitor. The clock monitor resets the device when the
following conditions are met:
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• The clock monitor is enabled (MCG_C6[CME] = 1)
• The MCG's external reference clock falls outside of the expected frequency range,
depending on the MCG_C2[RANGE] bit
Pin wakeup and error condition flags are cleared in the LLWU
and module wakeup flags are required to be cleared in the
peripheral module. Refer to the individual peripheral
specifications for more information.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
NOTE
Freescale Semiconductor, Inc.