MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1361

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

46.3.5 I
The I2S Control Register (CR) sets up the I2S. I2S reset is controlled by bit 0 in the CR.
I2S operating modes are also selected in this register (except AC97 mode which is
selected in the ACNT register).
Addresses: I2S0_CR is 4002_F000h base + 10h offset = 4002_F010h
Freescale Semiconductor, Inc.
Reset
Reset
RFRCLKDIS
SYNCTXFS
Bit
Bit
W
W
Reserved
R
R
31–13
Field
Field
12
11
31
15
0
0
2
S Control Register (I2Sx_CR)
30
14
0
0
0
FIFOs are in use, data is transferred to each data register alternately. RX1 can only be used in two-
channel mode of operation.
This read-only field is reserved and always has the value zero.
SYNCTXFS bit provides a safe window for CR[TE] to be visible to the internal circuit which is just after FS
occurrence. When SYNCTXFS is set, CR[TE] gets latched on FS occurrence and latched CR[TE] is used
to enable/disable I
CR[TE] is changed within 2 bit-clock cycles of FS occurrence, there is high probability that CR[TE] will be
latched on next FS.
NOTE: With TFRCLKDIS feature on, CR[TE] is used directly to enable transmitter in following cases (i)
This bit has no relevance in gated mode and AC97 mode.
0
1
Receive Frame Clock Disable.
CR[TE] not latched with FS occurrence and used directly for transmitter enable/disable.
CR[TE] latched with FS occurrence and latched-TE used for transmitter enable/disable.
29
13
0
0
Sync mode and Rx disabled (ii) Async Mode. Latched-TE is used to disable the transmitter.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
I2Sx_RX1 field descriptions (continued)
2
S transmitter. CR[TE] needs setup of 2 bit-clock cycles before occurrence of FS. If
27
11
0
0
I2Sx_CR field descriptions
Table continues on the next page...
26
10
0
0
25
0
0
9
24
0
0
8
0
Description
Description
23
0
0
7
I2SMODE
22
0
0
6
Chapter 46 Integrated interchip sound (I2S)
21
0
0
5
SYN
20
0
0
4
NET
19
0
0
3
RE
18
0
0
2
TE
17
0
0
1
1361
16
0
0
0