MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1017

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
23–19
TASD
Field
1. The number of the last remaining available mailboxes is defined by the least value between the
2. If Rx Individual Mask Registers are not enabled then all Rx FIFO filters are affected by the Rx FIFO
Tx Arbitration Start Delay
This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the
first bit of CRC field on CAN bus. This field can only be written in Freeze mode as it is blocked by
hardware in other modes.
This field is useful to optimize the transmit performance based on factors such as: peripheral/serial clock
ratio, CAN bit timing and number of MBs. The duration of an arbitration process, in terms of CAN bits, is
directly proportional to the number of available MBs and CAN baud rate and inversely proportional to the
peripheral clock frequency.
The optimal arbitration timing is that in which the last MB is scanned right before the first bit of the
Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial clock ratio is high
and the CAN baud rate is low then the arbitration can be delayed and vice-versa.
If TASD is 0 then the arbitration start is not delayed, thus the CPU has less time to configure a Tx MB for
the next arbitration, but more time is reserved for arbitration. In the other hand, if TASD is 24 then the
CPU can configure a Tx MB later and less time is reserved for arbitration.
If too little time is reserved for arbitration the FlexCAN may be not able to find winner MBs in time to
compete with other nodes for the CAN bus. If the arbitration ends too much time before the first bit of
Intermission field then there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
not the best to be transmitted.
The optimal configuration for TASD can be calculated as:
TASD = 25 - {f
where:
0x9
0xA
0xB
0xC
0xD
0xE
0xF
RFFN[3:
parameter NUMBER_OF_MB minus 1 and the MCR[MAXMB] field.
Global Mask.
• f
• f
• MAXMB is the value in CTRL1[MAXMB] field;
• RFEN is the value in CTRL1[RFEN] bit;
• RFFN is the value in CTRL2[RFFN] field;
• PSEG1 is the value in CTRL1[PSEG1] field;
0]
CANCLK
SYS
is the peripheral clock, in Hz;
80
88
96
104
112
120
128
CANx_CTRL2 field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Number
filters
is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in Hz;
of Rx
FIFO
{f
CANCLK
SYS
x [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] x (PRESDIV+1)}
MB 0-25
MB 0-27
MB 0-29
MB 0-31
MB 0-33
MB 0-35
MB 0-37
occupied by Rx
Table continues on the next page...
x [MAXB + 3 - (RFEN x 8) - (RFEN x RFFN x 2)] x 2} /
FIFO and ID
Filter Table
Message
Buffers
MB 26-63
MB 28-63
MB 30-63
MB 32-63
MB 34-63
MB 36-63
MB 38-63
Mailboxes
Remaining
Description
Available
1
Elements 0-25
Elements 0-27
Elements 0-29
Elements 0-31
Elements 0-31
Elements 0-31
Elements 0-31
Individual Masks
Rx FIFO ID Filter
Table Elements
Affected by Rx
Chapter 41 CAN (FlexCAN)
2
Elements 26-79
Elements 28-87
Elements 30-95
Elements 32-103
Elements 32-111
Elements 32-119
Elements 32-127
FIFO Global Mask
Rx FIFO ID Filter
Table Elements
Affected by Rx
1017
2