MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 883

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

36.4.12 Inverting
The invert functionality swaps the signals between channel (n) and channel (n+1)
outputs. The inverting operation is selected when (FTMEN = 1), (QUADEN = 0),
(DECAPEN = 0), (COMBINE = 1), (COMP = 1), (CPWMS = 0), and (INVm = 1),
where m represents a channel pair. The INVm bit in INVCTRL register is updated with
its buffer value according to
In high-true (ELSnB:ELSnA = 1:0) combine mode, the channel (n) output is forced low
at the beginning of the period (FTM counter = CNTIN), forced high at the channel (n)
match and forced low at the channel (n+1) match. If the inverting is selected, the channel
(n) output behavior is changed to force high at the beginning of the PWM period, force
low at the channel (n) match and force high at the channel (n+1) match. See the following
figure.
Note that the ELSnB:ELSnA bits value should be consider since that they define the
active state of the channels outputs. In low-true (ELSnB:ELSnA = X:1) combine mode,
the channel (n) output is forced high at the beginning of the period, forced low at the
channel (n) match and forced high at the channel (n+1) match. In the case the inverting is
selected the channels (n) and (n+1) present waveforms as shown in the following figure.
Freescale Semiconductor, Inc.
channel (n+1) output
channel (n+1) output
before the inverting
before the inverting
channel (n) output
after the inverting
NOTE
INV(m) bit selects the inverting to the pair channels (n) and (n+1).
INVCTRL register
channel (n) output
write 1 to INV(m) bit
after the inverting
synchronization
channel (n+1) match
INV(m) bit buffer
channel (n) match
FTM counter
Figure 36-225. Channels (n) and (n+1) Outputs After the Inverting in High-True
INV(m) bit
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
(ELSnB:ELSnA = 1:0) Combine Mode
INVCTRL Register Synchronization
Chapter 36 FlexTimer (FTM)
883