MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 563

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The cache entries, both data and tag/valid, can be read at any time.
The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and
the sets are numbered 0-7. The following table elaborates on the tag/valid and data
entries.
Freescale Semiconductor, Inc.
Control registers:
PFAPR, PFB0CR,
PFB1CR
Cache registers
Tag
Data
storage
Cache
Registers
100h
200h
Based at
offset
Program the registers only while the flash controller is idle (for
example, execute from RAM). Changing configuration settings
while a flash access is in progress can lead to non-deterministic
behavior.
Accesses to unimplemented registers within the FMC's 4 KB
address space return a bus error.
System software is required to maintain memory coherence
when any segment of the flash cache is programmed. For
example, all buffer data associated with the reprogrammed flash
should be invalidated. Accordingly, cache program visible
writes must occur after a programming or erase event is
completed and before the new memory image is accessed.
Supervisor (privileged)
mode or user mode
Supervisor (privileged)
mode or user mode
13'h0, tag[18:6], 5'h0, valid
Upper or lower word of data
Contents of 32-bit read
Table 27-3. Program visible cache registers
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Mode
Table 27-2. FMC register access
Read access
32 bits
32 bits
In TAGVDWxSy, x denotes the way
and y denotes the set.
In DATAWxSyU and DATAWxSyL,
x denotes the way, y denotes the
set, and U and L represent upper
and lower word, respectively.
NOTE
NOTE
NOTE
Length
Nomenclature
Supervisor (privileged)
mode only
Supervisor (privileged)
mode only
Chapter 27 Flash Memory Controller (FMC)
Mode
Write access
TAGVDW2S0 is the 13-bit
tag and 1-bit valid for cache
entry way 2, set 0.
DATAW1S0U represents bits
[63:32] of data entry way 1,
set 0, and DATAW1S0L
represents bits [31:0] of data
entry way 1, set 0.
Nomenclature example
8, 16, or 32 bits
32 bits
Length
563