MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 415

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
4000_917C
4000_917E
4000_917E
4000_918C
4000_919C
4000_919E
4000_919E
4000_9178
4000_9180
4000_9184
4000_9186
4000_9188
4000_9188
4000_9188
4000_9190
4000_9194
4000_9196
4000_9196
4000_9198
Absolute
address
(hex)
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD11_DLASTSGA)
TCD Control and Status (DMA_TCD11_CSR)
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD11_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD11_BITER_ELINKNO)
TCD Source Address (DMA_TCD12_SADDR)
TCD Signed Source Address Offset (DMA_TCD12_SOFF)
TCD Transfer Attributes (DMA_TCD12_ATTR)
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD12_NBYTES_MLNO)
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD12_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD12_NBYTES_MLOFFYES)
TCD Last Source Address Adjustment
(DMA_TCD12_SLAST)
TCD Destination Address (DMA_TCD12_DADDR)
TCD Signed Destination Address Offset
(DMA_TCD12_DOFF)
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD12_CITER_ELINKYES)
DMA_TCD12_CITER_ELINKNO
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD12_DLASTSGA)
TCD Control and Status (DMA_TCD12_CSR)
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD12_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD12_BITER_ELINKNO)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Register name
DMA memory map (continued)
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
(in bits)
Width
32
16
16
16
32
16
16
32
32
32
32
32
16
16
16
32
16
16
16
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Section/
21.3.28/
21.3.29/
21.3.30/
21.3.31/
21.3.17/
21.3.18/
21.3.19/
21.3.20/
21.3.21/
21.3.22/
21.3.23/
21.3.24/
21.3.25/
21.3.26/
21.3.27/
21.3.28/
21.3.29/
21.3.30/
21.3.31/
page
449
450
452
453
441
442
442
443
444
445
446
446
447
447
448
449
450
452
453
415