MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1111

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

42.4.7 Interrupts/DMA Requests
The DSPI has several conditions that can only generate interrupt requests and two
conditions that can generate interrupt or DMA requests. The following table lists these
conditions.
Each condition has a flag bit in the DSPI Status Register (SR) and an Request Enable bit
in the DSPI DMA/Interrupt Request Select and Enable Register (RSER). The TX FIFO
Fill Flag (TFFF) and RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA
requests depending on the TFFF_DIRS and RFDF_DIRS bits in the RSER.
The DSPI module also provides a global interrupt request line, which is asserted when
any of individual interrupt requests lines is asserted.
42.4.7.1 End of Queue Interrupt Request
The End of Queue Request indicates that the end of a transmit queue is reached. The End
of Queue Request is generated when the EOQ bit in the executing SPI command is set
and the EOQF_RE bit in the RSER is set.
Freescale Semiconductor, Inc.
End of Queue (EOQ)
TX FIFO Underflow
Transfer Complete
RX FIFO Overflow
RX FIFO Drain
This interrupt request is generated when the last bit of the SPI
frame with EOQ bit set is transmitted.
TX FIFO Fill
Condition
Table 42-86. Interrupt and DMA Request Conditions
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
NOTE
EOQF
RFOF
RFDF
TFUF
TFFF
TCF
Flag
Interrupt
Yes
Yes
Yes
Yes
Yes
Yes
Chapter 42 SPI (DSPI)
DMA
Yes
Yes
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