MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 597

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

28.33.2 Flash Configuration Register (FTFL_FCNFG)
This register provides information on the current functional state of the FTFL module.
The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. SWAP,
PFLSH, RAMRDY are read-only status bits . The unassigned bits read as noted and are
not writable. The reset values for the SWAP, PFLASH, RAMRDY bits are determined
during the reset sequence.
Address: FTFL_FCNFG is 4002_0000h base + 1h offset = 4002_0001h
Freescale Semiconductor, Inc.
RDCOLLIE
ERSAREQ
MGSTAT0
Reserved
CCIE
Field
Reset
Field
3–1
Read
Write
0
7
6
5
Bit
CCIE
This read-only field is reserved and always has the value zero.
Memory Controller Command Completion Status Flag
The MGSTAT0 status flag is set if an error is detected during execution of an FTFL command or during
the flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the
other error flags in this register.
The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution
when CCIF=1 and before the next command has been launched. At some point during the execution of
"command-N+1," the previous result is discarded and any previous error is cleared.
Command Complete Interrupt Enable
The CCIE bit controls interrupt generation when an FTFL command completes.
0
1
Read Collision Error Interrupt Enable
The RDCOLLIE bit controls interrupt generation when an FTFL read collision error occurs.
0
1
Erase All Request
7
0
Command complete interrupt disabled
Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF]
flag is set.
Read collision error interrupt disabled
Read collision error interrupt enabled. An interrupt request is generated whenever an FTFL read
collision error is detected (see the description of FSTAT[RDCOLERR]).
RDCOLLIE
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
FTFL_FSTAT field descriptions (continued)
0
6
FTFL_FCNFG field descriptions
ERSAREQ
Table continues on the next page...
0
5
ERSSUSP
0
4
Description
Description
SWAP
0
3
Chapter 28 Flash Memory Module (FTFL)
PFLSH
0
2
RAMRDY
0
1
EEERDY
0
0
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