MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 282

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Introduction
13.1.2.2 Run Modes
The device contains two different run modes:
13.1.2.2.1 Run Mode
This is the normal operating mode for the device.
This mode is selected after any reset. When the ARM processor exits reset, it sets up the
stack, program counter (PC), and link register (LR):
To reduce power in this mode, disable unused modules by clearing the peripherals
corresponding clock gating control bit in the SIM's registers.
13.1.2.2.2 Very Low Power Run (VLPR) Mode
In VLPR, the on-chip voltage regulator is put into a stop mode regulation state. In this
state, the regulator is designed to supply enough current to the MCU over a reduced
frequency. To further reduce power in this mode, disable the clocks to unused modules in
the peripherals' corresponding clock gating control bits in the SIM's registers.
Before entering this mode, the following conditions must be met:
282
• Run
• Very low power run (VLPR)
• The processor reads the start SP (SP_main) from vector-table offset 0x000
• The processor reads the start PC from vector-table offset 0x004
• LR is set to 0xFFFF_FFFF.
• One of two clock sources selected:
• The system, bus, and core frequency is 2 MHz or less.
• Flash frequency is 1 MHz or less.
• Mode protection must be set to allow VLP modes (AVLP = 1).
Transition #
11
• Either BLPE is the selected clock mode for the MCG or
• BLPI with the 2MHz IRC.
Table 13-2. Power mode transition triggers (continued)
VLPR
From
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
VLLS(3,2,1)
To
LPLLSM = (see PMCTRL register description for VLLS
configuration),
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, controlled in System Control Register in ARM core
Trigger Conditions
Freescale Semiconductor, Inc.