MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1240

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Application information
If the intent of clearing the interrupt is such that it does not reassert, the interrupt service
routine must remove or clear the condition that originally caused the interrupt to assert
prior to clearing the interrupt. There are multiple ways that this can be accomplished
including ensuring that an event that results in the wait timer resetting occurs such as the
transmission of another packet.
44.8.10 Legacy and reverse compatibility considerations
Recent versions of the UART have added several new features. Whenever reasonably
possible reverse compatibility was maintained, however, in some cases this was either not
feasible or the behavior was deemed as not intended. This section describes several
differences to legacy operation that resulted from these recent enhancements. If
application codes from previous versions is used, they should be reviewed and modified
to take the following items into account. Depending on the application code, additional
items that are not listed here may also need to be considered.
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4. After the WT interrupt has been cleared, the smartcard remains unresponsive. At
1. Various reserved registers and register bits were used (i.e. MSFB and M10).
2. This module now generates an error when invalid address spaces are used.
3. While documentation indicated otherwise, in some cases it was possible for
4. The S1[OR] flag will only be set if the data buffer (FIFO) does not have sufficient
5. Previously when the C2[RWU] was set (and WAKE = 0), the IDLE flag could
cycle 9701 the WT interrupt will reasserted.
S1[IDLE] to assert even if S1[OR] was set.
room. Previously, the data buffer was always a fixed size of one and the S1[OR] flag
would set so long as the S1[RDRF] flag was set even if there was room in the data
buffer. While the clearing mechanism is has remained the save for the S1[RDRF]
flag, keeping the OR flag assertion tied to the RDRF event rather than the data buffer
being full would have greatly reduced the usefulness of the buffer when its size is
larger than one.
reassert up to every bit period causing an interrupt and requiring the host processor to
reassert the C2[RWU] bit. This behavior has been modified. Now, when the
C2[RWU] is set (and WAKE = 0) at least one non-idle bit must be detected before an
idle can be detected.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.