MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 16

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Section Number
20.1
20.2
20.3
20.4
20.5
21.1
21.2
21.3
16
Introduction...................................................................................................................................................................387
20.1.1
20.1.2
20.1.3
External signal description............................................................................................................................................389
Memory map/register definition...................................................................................................................................389
20.3.1
Functional description...................................................................................................................................................391
20.4.1
20.4.2
20.4.3
Initialization/application information...........................................................................................................................395
20.5.1
20.5.2
Introduction...................................................................................................................................................................399
21.1.1
21.1.2
21.1.3
Modes of operation.......................................................................................................................................................403
Memory map/register definition...................................................................................................................................403
21.3.1
21.3.2
21.3.3
21.3.4
21.3.5
Overview......................................................................................................................................................387
Features........................................................................................................................................................388
Modes of operation......................................................................................................................................388
Channel Configuration Register (DMAMUX_CHCFGn)...........................................................................390
DMA channels with periodic triggering capability......................................................................................391
DMA channels with no triggering capability...............................................................................................394
"Always enabled" DMA sources.................................................................................................................394
Reset.............................................................................................................................................................395
Enabling and configuring sources................................................................................................................395
Block diagram..............................................................................................................................................399
Block parts...................................................................................................................................................400
Features........................................................................................................................................................402
Control Register (DMA_CR).......................................................................................................................418
Error Status Register (DMA_ES)................................................................................................................420
Enable Request Register (DMA_ERQ).......................................................................................................422
Enable Error Interrupt Register (DMA_EEI)...............................................................................................424
Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................426
Direct memory access multiplexer (DMAMUX)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Direct Memory Access Controller (eDMA)
Chapter 20
Chapter 21
Title
Freescale Semiconductor, Inc.
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