MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 194

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The Debug Port
The debug port comes out of reset in standard JTAG mode and is switched into either
cJTAG or SWD mode by the following sequences. Once the mode has been changed,
unused debug pins can be reassigned to any of their alternative muxed functions.
9.2.1 JTAG-to-SWD change sequence
9.2.2 JTAG-to-cJTAG change sequence
194
1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111_1001_1110_0111 (MSB
3. Send more than 50 TCK cycles with TMS (SWDIO) =1
1. Reset the debug port
transmitted first)
TDO
TDI
TCK
TMS
See the ARM documentation for the CoreSight DAP Lite for
restrictions.
J TAGNSW
TDO
TDI
SWCLKTCK
SWDITMS
SWDO
SWDOEN
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
TRACESWO
Figure 9-2. Modified Debug Port
(1’b1 = 4-pin J TAG)
(1’b0 = 2-pin cJ TAG)
1’b1
S WD/ J TAG
S ELECT
A
NOTE
TDI TDO PEN
TDO
TDI
nTRST
TC K
TMS_OUT
TMS_OUT_OE
TMS_IN
IR==BYPASS or IDC ODE
CJ TAG
4’b1111 or 4’b1110
nSYS_TRST
nSYS_TDO
nSYS_TC K
nSYS_TMS
A
nSYS_TDI
IR==BYPASS or IDC ODE
4’b1111 or 4’b0000
jtag_updateinstr[3:0]
TDI
nTRST
TC K
TMS
TDO
J TAGir[3:0]
Freescale Semiconductor, Inc.
J TAGC
DAP Bus
To Test
Resources
AHB-AP
MDM-AP