MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 362

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
362
Reserved
Reserved
Reserved
Reserved
M4WE
M3SM
M3UM
M2SM
M2UM
M1SM
M1UM
M4RE
22–21
20–18
16–15
14–12
10–9
Field
8–6
25
24
23
17
11
5
0
1
Bus master 4 read enable.
0
1
Bus master 4 write enable
0
1
This field is reserved.
This bit must be written with a zero.
Bus master 3 supervisor mode access control
Defines the access controls for bus master 3 in supervisor mode
00
01
10
11
Bus master 3 user mode access control
Defines the access controls for bus master 3 in user mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions.
0
1
This field is reserved.
This bit must be written with a zero.
Bus master 2 supervisor mode access control
See M3SM description.
Bus master 2 user mode access control
See M3UM description.
This field is reserved.
This bit must be written with a zero.
Bus master 1 supervisor mode access control
See M3SM description.
Bus master 1 user mode access control
See M3UM description.
This field is reserved.
This bit must be written with a zero.
Bus master 5 writes terminate with an access error and the write is not performed
Bus master 5 writes allowed
Bus master 4 reads terminate with an access error and the read is not performed
Bus master 4 reads allowed
Bus master 4 writes terminate with an access error and the write is not performed
Bus master 4 writes allowed
An attempted access of that mode may be terminated with an access error (if not allowed by another
descriptor) and the access not performed.
Allows the given access type to occur
r/w/x; read, write and execute allowed
r/x; read and execute allowed, but no write
r/w; read and write allowed, but no execute
Same as user mode defined in M3UM
MPU_RGDAACn field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Freescale Semiconductor, Inc.