MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1390

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Reset
Memory map/register definition
46.3.19 I
Addresses: I2S0_ACCST is 4002_F000h base + 50h offset = 4002_F050h
46.3.20 I
Addresses: I2S0_ACCEN is 4002_F000h base + 54h offset = 4002_F054h
1390
Bit
Bit
W
W
R
R
Reserved
31
31
0
0
ACCST
RMSK
31–10
31–0
Field
Field
9–0
30
30
0
0
29
29
0
0
28
28
0
0
2
2
S AC97 Channel Status Register (I2Sx_ACCST)
S AC97 Channel Enable Register (I2Sx_ACCEN)
Receive Mask.
These bits indicate which slot has been masked in the current frame. The Core can write to this register to
control the time slots in which the I
time slot in the frame. RMSK register value must be set before enabling Receiver.Receive mask bits
should not be used in I2S Slave mode of operation.
0
1
This read-only field is reserved and always has the value zero.
AC97 Channel Status.
These bits indicate which data slot has been enabled in AC97 variable mode operation. This register is
updated in case the core enables/disables a channel through a write to ACCEN/ACCDIS register or the
external codec enables a channel by sending a `1' in the corresponding SLOTREQ bit. Bit [0] corresponds
to the first data slot in an AC97 frame (Slot #3) and Bit [9] corresponds to the tenth data slot (slot #12).
The contents of this register only have relevance while the I
to this register result in an error response on the IP interface.
0
1
27
27
0
0
Valid Time Slot.
Time Slot masked (no data received in this time slot).
Data channel disabled.
Data channel enabled.
26
26
0
0
25
25
0
0
24
24
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
23
0
0
22
22
0
0
I2Sx_ACCST field descriptions
I2Sx_RMSK field descriptions
21
21
0
0
0
0
20
20
0
0
19
19
0
0
2
18
18
0
0
S receives data. Each bit has info corresponding to the respective
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
2
S is operating in AC97 variable mode. Writes
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
ACCEN
ACCST
0
0
5
5
0
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
0
0
0
0