MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 363

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

18.4 Functional Description
In this section, the functional operation of the MPU is detailed, including the operation of
the access evaluation macro and the handling of error-terminated bus cycles.
18.4.1 Access Evaluation Macro
The basic operation of the MPU is performed in the access evaluation macro, a hardware
structure replicated in the two-dimensional connection matrix. As shown in the following
figure, the access evaluation macro inputs the crossbar bus address phase signals and the
contents of a region descriptor (RGDn) and performs two major functions: region hit
determination and detection of an access protection violation. The following figure shows
a functional block diagram.
Freescale Semiconductor, Inc.
M0SM
M0UM
Field
4–3
2–0
Bus master 0 supervisor mode access control
See M3SM description.
Bus master 0 user mode access control
See M3UM description.
Address
MPU_RGDAACn field descriptions (continued)
Figure 18-80. MPU Access Evaluation Macro
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
(hit AND error)
MPU_EDRn
≥
start
hit_b
≥
Description
≥
≤
Access not allowed
(no hit OR error)
end
error
Chapter 18 Memory Protection Unit (MPU)
r,w,x
RGDn
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