MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1359

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Reset
46.3.1 I
The TX0 registers store the data to be transmitted by the I2S.
Addresses: I2S0_TX0 is 4002_F000h base + 0h offset = 4002_F000h
46.3.2 I
The TX1 registers store the data to be transmitted by the I2S.
Addresses: I2S0_TX1 is 4002_F000h base + 4h offset = 4002_F004h
Freescale Semiconductor, Inc.
Bit
Bit
W
W
R
R
31
31
0
0
31–0
31–0
Field
Field
TX0
TX1
30
30
0
0
29
29
0
0
2
2
28
28
S Transmit Data Registers 0 (I2Sx_TX0)
0
S Transmit Data Registers 1 (I2Sx_TX1)
0
I2S transmit data
I
first word of their respective Tx FIFOs. Data written to these registers transfers to the transmit shift
register (TXSR), when shifting of the previous data is complete. If both FIFOs are in use, data alternately
transfers from TX0 and TX1 to TXSR. TX1 can only be used in two-channel mode. Multiple writes to the
TX registers do not result in the previous data being over-written by the subsequent data. Instead they are
ignored. Protection from over-writing is present irrespective of whether the transmitter is enabled or not.
Example: If Tx FIFO0 is in use and you write Data1 - 16 to TX0, Data16 does not overwrite Data1. Data1 -
15 are stored in the FIFO while Data16 is discarded. Example: If Tx FIFO0 is not in use and you write
Data1, Data2 to TX0, then Data2 does not overwrite Data1 and is discarded.
NOTE: Enable I
I2S transmit data
I
first word of their respective Tx FIFOs. Data written to these registers transfers to the transmit shift
register (TXSR), when shifting of the previous data is complete. If both FIFOs are in use, data alternately
transfers from TX0 and TX1 to TXSR. TX1 can only be used in two-channel mode. Multiple writes to the
TX registers do not result in the previous data being over-written by the subsequent data. Instead they are
ignored. Protection from over-writing is present irrespective of whether the transmitter is enabled or not.
27
27
2
2
0
0
S transmit data. These bits store the data to be transmitted by the I
S transmit data. These bits store the data to be transmitted by the I
26
26
0
0
25
25
0
0
24
24
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
23
0
0
2
S (CR[I2SEN]=1) before writing to the I
22
22
0
0
21
21
0
0
I2Sx_TX0 field descriptions
I2Sx_TX1 field descriptions
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
16
16
0
0
TX0
TX1
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
2
12
12
S transmit data registers.
0
0
Chapter 46 Integrated interchip sound (I2S)
11
11
0
0
10
10
0
0
2
2
S. These are implemented as the
S. These are implemented as the
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
1359
0
0
0
0