MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 694

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

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Quantity
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Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Functional description
31.4.5.6 Conversion time examples
The following examples use
through
31.4.5.6.1 Typical conversion time configuration
A typical configuration for ADC conversion is: 10-bit mode, with the bus clock selected
as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency
of 8 MHz, long sample time disabled and high speed conversion disabled. The
conversion time for a single conversion is calculated by using
information provided in
variables of
The resulting conversion time is generated using the parameters listed in the proceeding
table. Therefore, for a bus clock equal to 8 MHz and an ADCK equal to 8 MHz the
resulting conversion time is 3.75 µs.
31.4.5.6.2 Long conversion time configuration
A configuration for long ADC conversion is: 16-bit differential mode with the bus clock
selected as the input clock source, the input clock divide-by-8 ratio selected, a bus
frequency of 8 MHz, long sample time enabled, configured for longest adder, high speed
conversion disabled, and average enabled for 32 conversions. The conversion time for
this conversion is calculated by using
31-107
694
AverageNum
AverageNum
HSCAdder
SFCAdder
SFCAdder
LSTAdder
LSTAdder
through
Variable
Variable
Table
BCT
BCT
Figure
31-111.
Table
31-95.
31-111. The following table lists the variables of the
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 31-107
Table 31-112. Typical conversion time
Table 31-113. Typical conversion time
Figure 31-95
Table continues on the next page...
Figure 31-95
through
and the information provided in
5 ADCK cycles + 5 bus clock cycles
3 ADCK cycles + 5 bus clock cycles
Table
20 ADCK cycles
34 ADCK cycles
20 ADCK cycles
and the information provided in
31-111. The table below list the
Time
Time
32
1
0
0
Figure 31-95
Freescale Semiconductor, Inc.
Table 31-107
Figure
and the
31-95.
Table

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