MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 903

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The following figure shows an example of the dual edge capture – continuous mode used
to measure the positive polarity pulse width. The DECAPEN bit selects the dual edge
capture mode, so it keeps set in all operation mode. While the DECAP bit is set the
configured measurements are made. The CH(n)F bit is set when the first edge of the
positive polarity pulse is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits.
The CH(n+1)F bit is set when the second edge of this pulse is detected, that is, the edge
selected by ELS(n+1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of
the pulse were captured and the C(n)V and C(n+1)V registers are ready for reading.
Freescale Semiconductor, Inc.
Note
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
- Problem 1: channel (n) input = 1, set DECAP, not clear CH(n)F, and clear CH(n+1)F.
- Problem 2: channel (n) input = 1, set DECAP, not clear CH(n)F, and not clear CH(n+1)F.
Figure 36-245. Dual Edge Capture – One-Shot Mode for Positive Polarity Pulse Width
channel (n) input
DECAPEN bit
(after the filter
channel input)
CH(n+1)F bit
DECAP bit
FTM counter
CH(n)F bit
C(n+1)V
C(n)V
clear CH(n+1)F
set DECAPEN
clear CH(n)F
set DECAP
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K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
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Measurement
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problem 1 problem 2
Chapter 36 FlexTimer (FTM)
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