MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 765

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

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Part Number:
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35.1.3 Back-to-back Acknowledgement Connections
PDB back-to-back operation acknowledgment connections are chip-specific. For
implementation, refer to the Chip Configuration information.
35.1.4 DAC External Trigger Input Connections
The implementation of DAC external trigger inputs is chip-specific. Refer to the Chip
Configuration information for details.
35.1.5 Block Diagram
This diagram illustrates the major components of the PDB.
Freescale Semiconductor, Inc.
• Y — Total number of Pulse-Out's.
• y — Pulse-Out number, valid value is 0 to Y-1.
The number of module output triggers to core are chip-specific.
For module to core output triggers implementation, refer to the
Chip Configuration information.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
NOTE
Chapter 35 Programmable Delay Block (PDB)
765

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