MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 876

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
If (SYNCMODE = 0), (SYNCHOM = 1) and (PWMSYNC = 0) then this
synchronization is done on the next enabled trigger event. If the trigger event was a
software trigger then the SWSYNC bit is cleared on the next selected loading point. If the
trigger event was a hardware trigger then the TRIGn bit is cleared according to
Trigger. Examples with software and hardware triggers follow.
If (SYNCMODE = 0), (SYNCHOM = 1) and (PWMSYNC = 1) then this
synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared
according to
876
Figure 36-216. OUTMASK Synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
Figure 36-215. OUTMASK Synchronization with (SYNCMODE = 0), (SYNCHOM = 1),
(SYNCHOM = 1), (PWMSYNC = 0), and (a Hardware Trigger Was Used)
Hardware
write 1 to SWSYNC bit
selected loading point
software trigger event
write 1 to TRIG0 bit
trigger 0 event
system clock
(PWMSYNC = 0) and (Software Trigger Was Used)
system clock
SWSYNC bit
TRIG0 bit
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Trigger. An example with a hardware trigger follows.
OUTMASK register is updated
OUTMASK register is updated and
TRIG0 bit is cleared
SWSYNC bit is cleared
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Hardware