MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 537

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
2. Then configure C5[PRDIV] to generate correct PLL reference frequency.
3. Then, FBE must transition either directly to PBE mode or first through BLPE mode
and then to PBE mode:
d. Loop until S[IREFST] is 0, indicating the external reference is the current source
b. BLPE/PBE: C6 = 0x40
d. PBE: Loop until S[PLLST] is set, indicating that the current source for the PLLS
c. Loop until S[OSCINIT] is 1, indicating the crystal selected by C2[EREFS] has
e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is
a. C5 = 0x01
a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1.
c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to
been initialized..
for the reference clock
selected to feed MCGOUTCLK
PBE mode.
clock is the PLL.
• C1[CLKS] set to 2'b10 in order to select external reference clock as system
• C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25
• C1[IREFS] cleared to 0, selecting the external reference clock and enabling
• C5[PRDIV] set to 5'b001, or divide-by-2 resulting in a pll reference
• C6[PLLS] set to 1, selects the PLL. At this time, with a C1[PRDIV] value of
• C6[VDIV] set to 5'b0000, or multiply-by-24 because 2 MHz reference * 24
clock source
kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL
the external oscillator.
frequency of 4 MHz/2 = 2 MHz.
2'b001, the PLL reference divider is 2 (see PLL External Reference Divide
Factor table), resulting in a reference frequency of 4 MHz/ 2 = 2 MHz. In
BLPE mode,changing the C6[PLLS] bit only prepares the MCG for PLL
usage in PBE mode.
= 48 MHz. In BLPE mode, the configuration of the VDIV bits does not
matter because the PLL is disabled. Changing them only sets up the multiply
value for PLL usage in PBE mode.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 24 Multipurpose Clock Generator (MCG)
537