MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1117

Manufacturer Part Number

MK30DN512ZVLK10

ARM Microcontrollers - MCU KINETIS 512K SLCD

Manufacturer

Freescale Semiconductor

ARM Cortex M4

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Operating Supply Voltage

1.71 V to 3.6 V

Operating Temperature Range

- 40 C to + 105 C

Package / Case

Mounting Style

Manufacturer

BOSTOCK HK LIMITED

Part Number:

MK30DN512ZVLK10

Manufacturer:

Freescale Semiconductor

42.5.5 Calculation of FIFO Pointer Addresses

Complete visibility of the TX and RX FIFO contents is available through the FIFO

registers, and valid entries can be identified through a memory mapped pointer and a

memory mapped counter for each FIFO. The pointer to the first-in entry in each FIFO is

memory mapped. For the TX FIFO the first-in pointer is the Transmit Next Pointer

(TXNXTPTR). For the RX FIFO the first-in pointer is the Pop Next Pointer

(POPNXTPTR). The following figure illustrates the concept of first-in and last-in FIFO

entries along with the FIFO Counter. The TX FIFO is chosen for the illustration, but the

concepts carry over to the RX FIFO. See

on the FIFO operation.

Freescale Semiconductor, Inc.

Receive First In First Out (RX FIFO) Buffering Mechanism

K30 Sub-Family Reference Manual, Rev. 6, Nov 2011

Table 42-88. Delay Values

Transmit First In First Out (TX FIFO) Buffering

Delay Prescaler Values

Chapter 42 SPI (DSPI)