MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1253

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
Reserved
Reserved
MSBSEL
RSPTYP
DTDSEL
CCCEN
CICEN
17–16
15–6
Field
20
19
18
5
4
This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0
for the following:
NOTE: In resume command, this bit shall be set, and other bits in this register shall be set the same as
0b
1b
Command Index Check Enable
If this bit is set to 1, the SDHC will check the index field in the response to see if it has the same value as
the command index. If it is not, it is reported as a command index error. If this bit is set to 0, the index field
is not checked.
0b
1b
Command CRC Check Enable
If this bit is set to 1, the SDHC shall check the CRC field in the response. If an error is detected, it is
reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked. The number of bits
checked by the CRC field value changes according to the length of the response.
0b
1b
This read-only field is reserved and always has the value zero.
Response Type Select
00b
01b
10b
11b
This read-only field is reserved and always has the value zero.
Multi/Single Block Select
This bit enables multiple block DAT line data transfers. For any other commands, this bit shall be set to 0.
If this bit is 0, it is not necessary to set the block count register.
0b
1b
Data Transfer Direction Select
This bit defines the direction of DAT line data transfers. The bit is set to 1 by the host driver to transfer
data from the SD card to the SDHC and is set to 0 for all other commands.
• Commands using only the CMD line (for example: CMD52).
• Commands with no data transfer, but using the busy signal on DAT[0] line (R1b or R5b, for
No data present
Data present
Disable
Enable
Disable
Enable
Single block
Multiple blocks
example: CMD38).
No response
Response length 136
Response length 48
Response length 48, check busy after response
when the transfer was initially launched. When the Write Protect switch is on, (i.e. the WPSPL bit
is active as ‘0’), any command with a write operation will be ignored. That is to say, when this bit
is set, while the DTDSEL bit is 0, writes to the register Transfer Type are ignored.
SDHC_XFERTYP field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Chapter 45 Secured digital host controller (SDHC)
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